Design Checklists and Reviews
Arm Design Checklists are a quick and easy way for engineers to verify critical aspects of design and add a layer of confidence in design success. Checklists help prevent errors, while ensuring the system is fit for purpose and follows recommended design guidelines from Arm.
| Product Family | Product Name |
|---|---|
| Cortex-A | Cortex-A7, Cortex-A32, Cortex-A34, Cortex-A35, Cortex-A53, Cortex-A55, Cortex-A65, Cortex-A65AE, Cortex-A72, Cortex-A73, Cortex-A76, Cortex-A78, Cortex-A78AE, Cortex-A510, Cortex-A710 |
| Cortex-R | Cortex-R5, Cortex-R8, Cortex-R52, Cortex-R52+, Cortex-R82 |
| Cortex-M | Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M52, Cortex-M55, Cortex-M85 |
| DynamIQ Shared Unit | DSU, DSU-110 |
| Ethos NPU | Ethos-U55 |
| Mali GPUs | Mali-G78AE, Mali-G310, Mali-G510 |
| Neoverse | Neoverse N2 |
| System IP | CoreLink DMA-330, CoreLink DMA-350, CoreLink GIC-400, CoreLink GIC-500, CoreLink GIC-600, CoreLink GIC-600AE, CoreLink GIC-625, CoreLink GIC-700, CoreLink MMU-600, CoreLink MMU-600AE, CoreLink MMU-700, CoreLink PCK-600, CoreSight SoC-400, CoreSight SoC-600 |
| Interconnect | CoreLink CI-700, CoreLink CMN-600, CoreLink CMN-600AE, CoreLink NI-700, CoreLink NIC-400, CoreLink NIC-450, CoreLink TZC-400, Neoverse CMN-650, Neoverse CMN-700 |
| Subsystem | Corstone-300, Corstone-310, Corstone-320, Corstone-1000 |
Our premium expert review service, Arm Design Reviews, helps you optimize your Arm-based system on chip (SoC) designs, using advice from the most experienced Arm engineers in the industry. Arm Design Reviews boost your Arm technology expertise and help your team design effectively to launch products quickly without risking quality.
By increasing the efficiency of communication and knowledge transfer between Arm engineers and your team, design reviews help to:
- Improve the quality of your design
- Shorten your design cycle and reduce time-to-market
- Reduce project risk
Design Reviews are designed to address project 'Hot Spots' in a typical SoC design flow.
